1. Field of Invention
The present invention relates to a method of fabricating a transistor in a semiconductor device, more particularly, to a method of fabricating a MOS transistor in a semiconductor device which reduces a fabricating cost, reducing the step difference between a surface of a source/drain and a gate, and improves a short channel effect, not by forming an additional epitaxial layer, but by forming trenches of which depths are different one another for defining both a gate area and a device isolation area and then by forming a device isolation layer and a gate successively.
2. Discussion of Related Art
As the size of semiconductor devices decrease, device density and performance can be greatly improved as more devices can be formed within a given area or footprint. On the contrary, the characteristics of a device may be degraded due to microscopic effects such as a short channel effect, a narrow channel effect and the like, caused by semiconductor devices being highly integrated and packed more closely together.
Short channel effect refers to when the channel length of a MOS transistor becomes shorter, and charges in a channel region are strongly affected by not only the gate voltage, but also by other charges such as, electrical fields and potential distributions of a depletion layer in the source/drain regions.
In a MOS transistor having a short channel, the voltage level in a channel region varies greatly since the drain voltage influences the channel and source regions, thereby reducing the threshold voltage and the voltage between a source and a drain to thus degrade the subthreshold voltage characteristics.
The decrease of the threshold voltage also depends on an impurity-doped density of the substrate, the depth of an impurity diffusion region of the source/drain, and the thickness of a gate oxide layer, as well as the drain voltage. In general, as the drain voltage increases, the substrate bias is made deeper, the gate oxide layer thickness increases, the substrate impurity concentration is decreased, or as the depths of the source/drain are made deeper, the threshold voltage decrease due to the short channel effect is magnified.
The subthreshold voltage characteristics refer to the relation between the drain current and the gate voltage in an inversion state produced when a predetermined voltage equal to or lower than the threshold voltage is applied to the gate electrode. Such characteristics play a great role in determining the performance of a MOS transistor as a switching device. Particularly in a MOS memory requiring charge storage, critical malfunctions of the device are caused by charge loss due to leakage current if the subthreshold voltage characteristics are poor.
Moreover, the voltage between the source and drain, which determines the limit of the source voltage by which a MOS transistor having a short channel can operate, depends greatly on the channel length. This voltage is decided by a punch-through effect of the short channel. A punch-through effect refers to the state in which the depletion layers of the source and drain are connected together, and is affected by the characteristics of the substrate surface or the internal conditions of the substrate.
In the related art, such short channel effect is improved by defining a device isolation area and a device active area with a trench type field oxide layer, then forming a gate oxide layer and a gate on the silicon substrate, and then selectively growing a mono-crystalline layer in a epitaxial manner on exposed regions of the active layer of the substrate so that the regions where the source and drain are to be formed protrude above the substrate surface.
FIG. 1A to FIG. 1C show cross-sectional views of fabricating a MOS transistor in a semiconductor device according to the related art.
Referring to FIG. 1A, a device isolation area and an active area are defined in a silicon substrate 10 of a first conductive type semiconductor by forming a device isolating layer, i.e., a field oxide layer 11 using shallow trench isolation (STI). Particularly after a trench has been formed by selectively etching a predetermined portion of the substrate, a field oxide layer 11 is formed by filling the trench with an insulator such as silicon oxide or the like. Alternatively, the oxide layer 11 may be formed by selectively oxidizing a predetermined portion of the silicon substrate 10 by local oxidation of silicon (LOGOS). An oxide layer used for a gate insulating layer 12 is formed by thermally oxidizing an exposed surface of the substrate 10. Next, a doped polysilicon layer, used for an electrode, is formed on the oxide layer by chemical vapor deposition (hereinafter CVD). After the doped polysilicon layer has been coated with a photoresist, a photoresist pattern is formed by exposure and development using an exposure mask defining a gate electrode forming region. Successively, a gate electrode 13 and a gate insulating layer 12 are formed by selectively removing portions of the polysilicon layer and the oxide layer which are not covered with the photoresist pattern using an anisotropic etch method. Then, the photoresist pattern is removed by O2 ashing or the like.
Referring to FIG. 1B, a layer 14 of oxide which insulates the gate electrode 13 is formed by oxidizing an exposed surface of the gate electrode 13. In this case, the protection layer 14 is used for electrically isolating the gate electrode 13 from the source/drain which will later be formed in an epitaxial layer. Then, a mono-crystalline layer 15 is grown on an exposed surface of the active area of the substrate 10 using an epitaxial method. Thus, the mono-crystalline layer 15 where the source/drain will be formed protrudes above the surface of the substrate 10, thereby reducing a step difference between the source/drain forming area and the gate electrode 13.
However, there is a disadvantage due to increased manufacturing costs in forming the mono-crystalline layer 15 using the epitaxial method. Referring to FIG. 1C, an ion-buried layer used for impurity diffusion regions for forming a source/drain, is formed by carrying out ion-implantation on the mono-crystalline layer 15 with second conductive type impurities using the gate electrode 13 and the protection layer 14 as an ion-implantation mask. Thereafter, a source and a drain of an impurity diffusion region 150 are formed by sufficiently diffusing the second conductive type impurity ions in the ion-buried layer by thermal treatment such as annealing or the like.
Then, as an option, a silicide layer 16 of WSix or the like may be formed on an exposed surface of the impurity diffusion region 150 to reduce contact resistance. In this case, the silicide layer 16 may be formed by a salicidation method.
Unfortunately, the method of fabricating a transistor in a semiconductor device according to the related art is expensive and thus not cost competitive compared to other conventional device manufacturing processes, because the forming of the source/drain formation region to protrude above the substrate comprising a mono-crystalline layer employs an expensive epitaxial method.
Accordingly, the present invention is directed to a method of fabricating a transistor in a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The present invention provides a method of fabricating a MOS transistor in a semiconductor device which reduces fabricating costs, reduces the step difference between the surface of the source/drain and the gate, and improves a short channel effect by forming trenches of different depths at predetermined portions of the substrate for defining both a gate formation area and a device isolation area, and then by forming a gate and a device isolation layer gate successively thereafter. An additional epitaxial layer need not be formed, thus manufacturing costs are reduced.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention as understood by those skilled in the art. Other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the present invention, as embodied and broadly described, the present invention includes the steps of forming a first trench and a second trench in a first conductivity type semiconductor substrate in which an active area and a device isolation area are defined. A gate forming area is defined in the active area, the first trench is formed to a first depth to define the device isolation area, and simultaneously, the second trench is formed to a second depth to define the gate forming area by removing predetermined portions of the substrate. A device isolation layer is formed by filling up the first trench with an insulator. Then, a gate insulating layer is formed on an inner surface of the second trench, filling up the second trench with a conductive substance wherein the second trench is covered with the gate insulating layer. Then, a pair of impurity diffusion regions of a second conductivity type are formed respectively in the active area of the substrate between the first and second trenches.
Preferably, the step of simultaneously forming a first trench and a second trench further includes the steps of forming an etch mask exposing only the device isolation area and the gate forming area of the semiconductor substrate; forming a sacrificial layer covering only the gate forming area of the exposed surfaces of the semiconductor substrate using a substance having a high etch selectivity ratio with the etch mask; implanting impurity ions into the exposed device isolation area of the semiconductor substrate to increase an etch rate of the semiconductor substrate; re-exposing the surface of the semiconductor substrate of the gate forming area by removing the sacrificial layer; and removing the exposed portions of the semiconductor substrate by predetermined depths in the device isolation area and the gate forming area.
More preferably, the method further includes the step of forming a silicide layer on the impurity diffusion regions. In another aspect, the present invention includes the steps of forming a first etch mask on a predetermined portion of a first conductivity type semiconductor substrate in which an active and a device isolation area are defined, wherein a gate forming area is defined in the active are and wherein the first etch mask is formed to expose the device isolation area; increasing an etch rate of the exposed device isolation area of the substrate by ion implantation; forming a second etch mask exposing the gate forming area of the semiconductor substrate by removing a portion of the first etch mask; simultaneously forming a first trench and a second trench removing portions of the substrate exposed by the second etch mask wherein the first and second trenches differ in depth and defines the device isolation area and the gate forming area, respectively; forming a device isolation layer by filling up the first trench with an insulator; forming a gate insulating layer on an inner surface of the second trench; forming a conductive layer on the second etch mask and device isolation layer including the second trench covered with the gate insulating layer; exposing the upper surfaces of the device isolation layer and the second etch mask by carrying out chemical/mechanical polishing on the conductive layer, wherein a gate formed of a potion of the conductive layer remaining only in the second trench; forming an additional insulating layer on an exposed surface of the gate; removing the second etch mask; and forming impurity diffusion regions of a second conductivity type respectively in the active area of the substrate between the first and second trenches.
Preferably, the step of exposing the upper surfaces of the device isolation layer and the second etch mask by carrying out chemical/mechanical polishing on the conductive layer wherein a gate formed of a portion of the conductive layer remaining only in the second trench further comprising the steps of forming a photoresist pattern covering over only the first trench on the conductive layer; leaving a portion of the conductive layer on the gate insulating layer in the second trench by removing the rest of the conductive layer not covered with the photoresist pattern; removing the photoresist pattern; and forming a gate by removing portions of the remaining conductive layer; the device isolation layer, and the gate insulating layer to expose a top surface of the second etch mask by planarization, wherein the gate is formed of the remaining conductive layer.
It is to be understood that both the foregoing general description and the following detailed description are only exemplary and explanatory, and are intended to provide further explanation of the invention as claimed.